Tuesday, October 9, 2007

CFP: First Workshop on Programmability Issues for Multi-Core Computers (MULTIPROG)


First Workshop on Programmability Issues for Multi-Core Computers (MULTIPROG)

Held in conjunction with the 3rd International Conference on High-Performance Embedded Architectures and Compilers (HiPEAC) Goteborg, Sweden, January 27, 2008

Goal of the Workshop
As computer manufacturers are embarking on the multi-core roadmap, which promises a doubling of the number of processors on a chip every other year, the programming community is faced with a severe dilemma. Until now, software has been developed with a single processor in mind and it needs to be parallelized to take advantage of the new breed of multi-core computers. As a result, progress in how to easily harness the computing power of multi-core architectures is in great demand.

This workshop aims to bring together, and cause fruitful interaction between, researchers interested in programming models and their implementation and in computer architecture with the common interest in advancing our knowledge how to simplify the task of parallelization of software for multi-core platforms. A wide spectrum of issues are central themes for this workshop such as what the future programming models should look like to accelerate software productivity and how it should be implemented at the runtime, the compiler, and the architecture level.

We will prioritize papers reporting on on-going work that address cross-cutting issues and that provide thought-provoking insights into the main themes. A special issue that contains the accepted papers is planned for the second issue of Transactions on HiPEAC in June 2008.

Topics of interest

Papers are sought on topics including, but not limited to:

* Multi-core architectures
o Architectural support for compilers/programming models
o Processor (core) architecture
o Memory system architecture
o Performance/power issues
* Programming models for multi-core architectures
o Language extensions
o Run-time systems
o Compiler optimizations and techniques
* Applications for multi-core architectures
o Methodologies
o Benchmarking


Eduard Ayguade Barcelona Supercomputing Center Spain eduard[at]ac.upc.edu
Roberto Gioiosa Barcelona Supercomputing Center Spain roberto.gioiosa[at]bsc.es
Per Stenstrom Chalmers University of Technology Sweden pers[at]chalmers.se
Osman Unsal Barcelona Supercomputing Center Spain osman.unsal[at]bsc.es

Important dates
Submission deadline: Oct 5, 2007
Notification to authors: Nov 16, 2007
Final version of accepted papers: Dec 7, 2007

Paper submission

Submitted papers should use the LNCS format and should be 12 pages maximum. Manuscript preparation guidelines can be found at the LNCS specification web site (go to -> For Authors -> Information for LNCS Authors).
In order to submit your paper go to http://multiprog.ac.upc.edu/CRP/.

Program committee

David Bernstein IBM Research Lab in Haifa Israel
Mats Brorsson KTH Sweden
Barbara Chapman University of Houston USA
Marcelo Cintra University of Edinburgh U.K.
Magnus Ekman Sun Microsystems USA
Pascal Felber University of Neuchatel Switzerland
Guang Gao University of Delaware USA
Roberto Georgi University of Siena Italy
Rachid Guerraoui EPFL Switzerland
Erik Hagersten Uppsala University Sweden
Michael Hohmuth AMD - Dresden Germany
Tim Harris Microsoft Research - Cambridge U.K.
Haoquiang Jin NASA Ames USA
Stefanos Kaxiras University of Patras Greece
Ami Marowka Shenkar College of Engineering and Design Israel
Milo Martin University of Pennsylvania USA
Dieter an Mey RWTH, Aachen Germany
Kathy O'Brien IBM Watson Research USA
Mitsuhisa Sato University of Tsukuba Japan
Sanjiv Shah Intel USA
Andre' Seznec IRISA France
Peng Wu IBM Watson Research USA

More details about the workshop can be found at http://multiprog.ac.upc.edu/

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